Fin field-effect transistors (FinFETs) typically include a source region and a drain region interconnected by fins which serve as a channel region of the device and a gate that surrounds at least a portion of each of the fins between the source region and the drain region. Epitaxy deposition is typically used to form the source region and the drain region. Dimensions of FinFET devices may be limited by various design considerations including available geographical space in a circuit for the FinFET device and required ratios of various devices in the circuit. In one example, in a static random access memory (SRAM) device, pull-up and pull-down devices must have widths (corresponding to heights in FinFET devices) of predetermined ratios with respect to each other. However, the device width for a FinFET device is determined by the number of fins multiplied by a fin height. Since the number of fins may be limited due to constraints on the size of the FinFET circuit, the device width ratio may be limited for fins with only height. Typically, different device widths are obtained by using different numbers of fins in different FinFETs. In some designs, it is desirable to change an active area of the fins to increase performance of the FinFET. For example, in a SRAM design, a p-type FET (pFET) having a smaller active area is desired to obtain a weaker PFET, which increases device stability. However, since typical pFET designs use only one fin, the number of fins may not be reduced to decrease the active area of the fins.